1.1. Field of the Invention
The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. Said first signal is the primary signal and the second signal is a stand-by signal for said computer system.
1.2. Description and Disadvantages of Prior Art
State-of-the-art clock switching is exemplarily disclosed at www.freescale.com/webapp/sps/site/.
The prior art Freescale MPC9993 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input clock signals. Upon detection of a failure (clock stuck HIGH or LOW for at least 1 period), the INP_BAD for that clock will be latched (H). If that clock is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated.
The prior art Freescale MPC9894 is a quad input redundant differential clock generator. The device contains logic for clock failure detection and auto switching for clock redundant applications. The generator uses a fully integrated PLL to generate clock signals from up to four redundant clock sources. The PLL multiplies the frequency of the input reference clock by one, two, four, eight or divides the reference clock by two or four. The frequency-multiplied clock signal drives four banks of two differential outputs, each bank allows an individual frequency-divider configuration. All outputs are phase-aligned and due to the external PLL feedback, the clock signals of all outputs are also phase-aligned to the selected input reference clock, providing virtually zero-delay capability.
A prior art multi-node system is depicted roughly in FIG. 1 with the focus directed to clock signal generation and distribution. The scheme given in FIG. 1 shows a prior art application with a standard ‘Dynamic Clock Switch Circuit’ (DCSC). The left box comprises two redundant pairs indexed 0 and 1 of oscillator 10 and synthesizer/Phase locked loop circuits 12 denoted as PLL. The clock signals as generated from an Oscillator are multiplied in frequency by said synthesizer/PLL circuits 12. A DCSC circuit 14 is provided for switching to the secondary clock signal, in case the primary clock signal would fail. DCSC 14 thus receives the multiplied clock signals and drives a plurality of N clock chips 18 provided on respective N nodes 15. A node is hereby understood to be a relatively large mainboard having, by way of example a number of 16, 32, or more processor chips implemented thereon. In a casing of a high-end server, for example a number of 10 nodes are arranged to build a mainboard tower.
Each processor chip 18 in turn comprises a fine clock signal distribution network for supplying said multiple processor chips with properly time-adjusted clock signals, in order to run the processors in highly synchronous operation modes.
The DCSC 14 thus allows a switch-over from the pair e.g. Oscillator 0/PLL 0 to the pair Oscillator 1/PLL 1, in case of a failure in pair 0. During this switch-over, the inner logic of DCSC 14 guarantees that the output of the DCSC 14 still generates valid clock signals, so that the processor chips 18 at the end of this outer clock distribution still get valid clock signals and continue operation.
The problem with this scheme, however, is that in case of a failure of the DCSC 14 itself or of the wiring 17 between DCSC and the clock chip the clock distribution will be interrupted and broken, and so the processor chips 15 will stop operation.
U.S. Pat. No. 6,675,307 provides a clock distribution, which resolves this problem for single-node computer systems. Disadvantageously, this system is not simply adaptable for multiprocessor or multi-node systems, as this would imply to implement many PLL circuits at each clock chip, which is not desired due to increased jitter and space consumption. Further disadvantageously, a large delay line is used, which results in decreased accuracy for the clock output. This decreased accuracy would reduce the system performance and therefore has to be avoided.
1.3. Objectives of the Invention
It is thus an objective of the present invention to provide a system and method for switching between two redundant clock signals in a multi-processor, multi-node computer system, wherein no outage time is required.